The present invention relates to a semiconductor memory and particularly to an arrangement which may be effectively applied to a static random access memory (hereinafter referred to as static RAM or SRAM) including memory cells comprising flip-flops. More specifically, the present invention relates to an arrangement which may be effectively applied to testing characteristics of static memory cells.
Generally, the static memory cells included in a static RAM include flip-flops as the storage means. Each flip-flop includes a pair of inverter circuits in which the input and output are cross-coupled. Each inverter circuit includes a load element and a drive element which are connected in series between the first and second operation power source voltages (V.sub.CC and V.sub.GND) of the static RAM. The load element is typically formed by a high resistance element of polycrystalline silicon (poly-Si) or a P channel metal-oxide-semiconductor field effect transistor (MOSFET), while the drive element is formed by an N channel MOSFET.
On the other hand, in order to obtain a static RAM of large capacity, a pair of load elements and a pair of drive elements included in each memory cell are arranged with regard to size and layout of each element to reduce the layout area of the memory cells. As a result, recently, the memory capacity of static RAMs has been improved to 256 kbits or even up to 1 Mbits through the progress in semiconductor manufacturing technology and the improvement in memory cell layout.
The testing of such large capacity memory devices and particularly the testing of memory cell characteristics requires a longer period of time due to its extensive memory capacity, resulting in an increase of testing cost and a resultant increase in product cost.